MOSFET power transistor having offset gate and drain pads to reduce capacitance

ABSTRACT

In an RF/microwave power amplifier comprising a linear array of MOSFET transistors in a semiconductor substrate, the transistors having gate and drain bond pads between adjacent transistors, drain to gate feedback capacitance is reduced by offsetting the drain bond pads from the gate bond pads. Bond wires to the drain bond pads extend in the offset direction from the drain bond pads, and bond wires to the gate bond pads extend from the gate bond pads in the opposite direction to reduce capacitive coupling between the bond wires and reduce the length of the bond wires.

BACKGROUND OF THE INVENTION

This invention relates generally to MISFET (MOSFET) transistors, andmore particularly the invention relates to a MOSFET structure havingreduced gate to drain feedback capacitance.

The MISFET transistor, more commonly known as a MOSFET, includes asource and drain region separated by a channel region with theconductance of the channel region controlled by a voltage bias appliedto a gate electrode over the channel. Ohmic contacts are made to each ofthe source, drain, and gate of a transistor in circuit applications.

Discrete MOSFET devices are well suited for RF/microwave powerapplications. The gate to drain feedback capacitance (C_(gd) or C_(rss))of any MOSFET transistor device must be minimized in order to maximizeRF signal gain and minimize signal distortion. The gate to drainfeedback capacitance is critical since it is effectively multiplied bythe voltage gain of the device, or C_(effective) =C_(rss) (1+gmR₁) wheregm is the transconductance and R₁, is the load impedance.

Attempts to minimize the gate to drain feedback capacitance includes theuse of a Faraday shield made of metal or polysilicon which is formedover the gate structure and typically is connected to the source region.See for example, Technical Digest IEDM Conference 1996, pgs. 87-90 whichdescribe a 2 GHz RF LDMOS transistor and pgs. 91-94 which describe a 1GHz RF LDMOS transistor. FIG. 1A shows a plurality of RF/microwave powerMOSFET transistors in a semiconductor body 12 with bonding pads providedbetween adjacent transistors with the bonding pads having capacitivecoupling as illustrated in FIG. 1B. In these devices a plurality ofMOSFET transistors are linearly arranged in a semiconductor body 12 withshared gate bond pads 16 and drain bond pads 15 provided betweenadjacent transistors on a major surface of a semiconductor body. All ofthe bond pads are generally linearly arranged, and bond wires 15, 17contact the respective drain pads and gate pads, as illustrated in theplan view of FIG. 1 of the drawing. The close proximity of the bond padsand the bond wires provides a coupling capacitance between the drain andgate which is not negligible. For example, the Crss component from gateto drain bond wires is estimated at greater than 10% of the totalgate-drain capacitance for a drain to source voltage greater than 10volts.

The present invention is directed to an integrated MOSFET transistordevice having reduced gate to drain feedback capacitance.

SUMMARY OF THE INVENTION

In accordance with the invention, an integrated MOSFET semiconductordevice includes a plurality of MOSFET transistors formed in asemiconductor body in a generally linear arrangement with eachtransistor having a drain bond pad and a gate bond pad on the devicesurface with each bond pad positioned between adjacent transistors. Thedrain bond pads are generally linearly arranged and the gate bond padsare generally linearly arranged and offset from the drain bond pads,thereby reducing gate to drain feedback capacitance. Bond wires to thedrain bond pads extend from the device surface in one direction, andbond wires to the gate bond pads extend from the device surface in asecond direction opposite to the first direction, thereby furtherreducing capacitive coupling. Preferably, the drain bond pads are offsetfrom the gate bond pads in the direction of the drain wire bonds.

In one embodiment, the bond pads are formed on thick oxide to reduce padto substrate capacitance with each bond pad shared by adjacenttransistors.

The invention and objects and features thereof will be more readilyapparent from the following detailed description and appended claimswhen taken with the drawing.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A and FIG. 1B are a plan view of an RF/microwave power MOSFETtransistor device and a schematic of gate to drain capacitive couplingin accordance with the prior art.

FIG. 2A and FIG. 2B are a plan view of an RF/microwave power MOSFETdevice in accordance with one embodiment of the present invention, andthe gate to drain capacitance thereof.

FIG. 3 is a section view of a portion of the device of FIG. 2Aillustrating the positioning of bond pads on thick field oxide inaccordance with one embodiment of the invention.

FIG. 4 is a plot of measured Crss vs. V_(dss) for standard bond pads andoffset bond pads in accordance with the invention.

DETAILED DESCRIPTION OF THE ILLUSTRATIVE EMBODIMENTS

FIG. 2A is a plan view of an RF/microwave power MOSFET device inaccordance with one embodiment of the present invention, and FIG. 2Billustrates the capacitive coupling between gate and drain bond pads andbond wires thereof. The arrangement of transistors 20 in a semiconductorbody 22 is similar to the arrangement of transistors 10 in semiconductorbody 12 of FIG. 1A, but in FIG. 2A the bond pads 24 are linearlyarranged and offset from the gate bond pads 26 with the offset of thedrain bond pads being in the direction of the drain bond wires 25. Thisoffset of the drain bond pads and wires from the gate bond pads andwires spaces the pads and wires further apart and thus reduces thecapacitive coupling between the source and drain bond pads and bondwires as illustrated in FIG. 2B. Further, since the bond pads are closerto the periphery of the die, the bond wire inductance is furtherreduced.

FIG. 3 is a section view of a portion of the transistor device of FIG.2A with the semiconductor body 22 comprising a P+ substrate and a P-epitaxial layer and the transistors 20 comprising LDMOS transistors. Tofurther reduce bond pad capacitance to the underlying substrate, thedrain bond pads 24 are formed on thick field oxide 30 between adjacenttransistors 20 with metal lines connecting the bond pads 24 to the drainregions 24' of the transistors. The gate bond pads 26 are preferablyformed over a deposited dielectric layer of silicon oxide and siliconnitride to minimize pad to substrate capacitance.

FIG. 4 is a plot illustrating measured gate to drain capacitance (Crss)versus drain to source voltage (V_(dss)) for offset bond pads inaccordance with the invention versus standard in-line bond pads. Crssfor the offset pads is consistently lower than Crss for standard padsover the voltage range with the reduction being approximately 7% forV_(dss) greater than 10 volts.

The reduction of gate to drain feedback capacitance using offset drainand gate bond pads in accordance with the invention is significant,particularly for RF and microwave power MOSFET transistors. The use ofoffset drain bond pads and gate bond pads significantly reduces thefeedback capacitance between the drain and gate regions. Further, nochange in process or device structure is required in implementing theinvention in existing product lines. Additionally, inductance of wirebonds can be reduced since the length of the wire bonds is less whenusing offset bond pads.

While the invention has been described with reference to specificembodiments, the description is illustrative of the invention as not tobe construed as limiting the invention. For example, the bond padseparation can be varied between adjacent transistors in a transistorarray. Thus, the description is illustrative of the invention and is notto be construed as limiting the invention. Various modifications andapplications may occur to those skilled in the art without departingfrom the true spirit and scope of the invention as defined by theappended claims.

What is claimed is:
 1. An RF microwave integrated lateral DMOS powersemiconductor transistor device with reduced bonding pad couplingcomprising:a) a semiconductor body having a major surface, b) aplurality of lateral DMOS transistors formed in the semiconductor bodyin a linear arrangement, c) each transistor having a drain bond pad anda gate bond pad on the major surface with each bond pad positionedbetween adjacent transistors, the drain bond pads being generallylinearly arranged and the gate bond pads being generally linearlyarranged and offset from the drain bond pads, thereby reducing gate todrain feedback capacitance.
 2. The integrated semiconductor transistordevice as defined by claim 1 wherein the offset is varied betweentransistors.
 3. The integrated semiconductor transistor device asdefined by claim 1 wherein each bond pad is shared by adjacenttransistors.
 4. The integrated semiconductor transistor device asdefined by claim 3 and further including bond wires contacting the bondpads.
 5. The integrated semiconductor transistor device as defined byclaim 4 wherein the bond wires to drain bond pads extend from the majorsurface in one direction, and the bond wires to the gate bond padsextend from the major surface in a second direction opposite to thefirst direction to thereby further reduce capacitive coupling of thewires and reduce length and inductance of the wires.
 6. The integratedsemiconductor transistor device as defined by claim 5 wherein the drainbond pads are offset from the gate bond pads in the one direction. 7.The integrated semiconductor transistor device as defined by claim 6 andfurther including a thick field oxide on the major surface, the drainbond pads being formed on the thick oxide to reduce pad to substratecapacitance.
 8. The integrated semiconductor transistor device asdefined by claim 7 and further including a deposited dielectric on themajor surface under the gate bond pads, the gate pads being formed onthick oxide to reduce substrate capacitance.
 9. The integratedsemiconductor transistor device as defined by claim 7 and furtherincluding a deposited dielectric on the major surface under the gatebond pads.
 10. The integrated semiconductor transistor device as definedby claim 1 and further including bond wires contacting the bond pads.11. The integrated semiconductor transistor device as defined by claim 9wherein the bond wires to the drain bond pads extend from the majorsurface in one direction and the bond wires to the gate bond pads extendfrom the major surface in a second direction opposite to the firstdirection thereby reducing capacitive coupling of the bond wires andreducing length and inductance of the wires.
 12. The integratedsemiconductor transistor device as defined by claim 10 wherein the drainbond pads are offset from the gate bond pads in the one direction. 13.The integrated semiconductor transistor device as defined by claim 1 andfurther including a thick field oxide on the major surface, the drainbond pads being formed on the thick oxide to reduce pad to substratecapacitance.
 14. The integrated semiconductor transistor device asdefined by claim 1 wherein said device comprises an RF/microwave poweramplifier.